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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a fiber optic receiver with quantizer and clock recovery and data retiming AD808 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 features meets ccitt g.958 requirements for stm-4 regeneratortype a meets bellcore tr- nwt-000253 requirements for oc-12 output jitter: 2.5 degrees rms 622 mbps clock recovery and data retiming accepts nrz data, no preamble required phase-locked loop type clock recovery no crystal required quantizer sensitivity: 4 mv level detect range: 10 mv to 40 mv, programmable single supply operation: +5 v or C5.2 v low power: 400 mw 10 kh ecl/pecl compatible output package: 16-lead narrow 150 mil soic frequency acquisition without false lock. this eliminates a reli- ance on external components such as a crystal or a saw filter, to aid frequency acquisition. the AD808 acquires frequency and phase lock on input data using two control loops that work without requiring external control. the frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. at frequency lock, the frequency error is zero and the frequency detector has no further effect. the phase acquisition control loop then works to ensure that the output phase tracks the input phase. a patented phase detector has virtually eliminated pat- tern jitter throughout the AD808. the device vco uses a ring oscillator architecture and patented low noise design techniques. jitter is 2.5 degrees rms. this low jitter results from using a fully differential signal architecture, power supply rejection ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the ic. the device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. the user sets the jitter peaking and acquisition time of the pll by choosing a damping factor capacitor whose value determines loop damping. ccitt g.958 type a jitter transfer require- ments can easily be met with a damping factor of 5 or greater. device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. shorting the damping factor capacitor, c d , brings the clock output frequency to the vco center frequency. the AD808 consumes 400 mw and operates from a single power supply at either +5 v or C5.2 v. functional block diagram signal level detector compensating zero vco retiming device loop filter f det s pin nin thradj sdout clkoutp clkoutn dataoutp dataoutn level detect comparator/ buffer AD808 phase-locked loop cf1 cf2 quantizer f det product description the AD808 provides the receiver functions of data quantiza- tion, signal level detect, clock recovery and data retiming for 622 mbps nrz data. the device, together with a pin diode/preamplifier combination, can be used for a highly inte- grated, low cost, low power sonet oc-12 or sdh stm-4 fiber optic receiver. the receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable thresh- old. the threshold is set with a single external resistor. the signal level detect circuit 3 db optical hysteresis prevents chatter at the signal level detect output. the pll has a factory trimmed vco center frequency and a frequency acquisition control loop that combine to guarantee
AD808Cspecifications rev. 0 C2C parameter condition min typ max units quantizerCdc characteristics input voltage range @ p in or n in 2.5 v s v input sensitivity, v sense p in Cn in , figure 1, ber = 1 10 C10 10 4.0 mv input overdrive, v od figure 1, ber = 1 10 C10 5 2.0 mv input offset voltage 1.0 mv input current 10 m a input rms noise ber = 1 10 C10 100 m v input peak-to-peak noise ber = 1 10 C10 1.5 mv quantizerCac characteristics upper C3 db bandwidth 600 800 mhz input resistance 10 k w input capacitance 2pf pulsewidth distortion 50 ps level detect level detect range r thresh = 22.1 k w 6.5 10 13.5 mv r thresh = 6.98 k w 13 18 23 mv r thresh = 0 w 28.5 40 45.5 mv response time dc coupled 0.1 1.5 m s hysteresis (electrical) r thresh = 22.1 k w (see figure 8) 5 9.0 db r thresh = 6.98 k w 3.0 5.1 9.0 db r thresh = 0 w 3.0 7.0 10.0 db sdout output logic high load = +3.2 ma 4.0 4.7 v sdout output logic low load = C3.2 ma 0.2 0.4 v phase-locked loop nominal center frequency 622.08 mhz capture range 620 624 mhz tracking range 620 624 mhz static phase error (see figure 7) 2 7 C1 prn sequence 22 81 degrees setup time (t su ) figure 2 550 900 ps hold time (t h ) figure 2 700 1050 ps phase drift 240 bits, no transitions 50 degrees jitter 2 7 C1 prn sequence 2.5 3.6 degrees rms 2 23 C1 prn sequence 2.5 3.6 degrees rms jitter tolerance f = 30 hz 3000 unit intervals f = 300 hz 24 300 unit intervals f = 25 khz 1.7 3.7 unit intervals f = 250 khz 0.28 0.56 unit intervals f = 5 mhz 0.18 0.45 unit intervals jitter transfer peaking (figure 14) c d = 0.47 m f 0.04 db bandwidth 333 450 khz acquisition time c d = 0.1 m f2 23 C1 prn sequence, t a = +25 c2 10 6 3 10 6 bit periods c d = 0.47 m fv cc = 5 v, v ee = gnd 8 10 6 12 10 6 bit periods power supply voltage v min to v max 4.5 5.5 volts power supply current v cc = 5.0 v, v ee = gnd, t a = +25 c 55 80 100 ma pecl output voltage levels output logic high, v oh t a = +25 c C1.2 C1.0 C0.7 volts output logic low, v ol referenced to v cc C2.2 C2.0 C1.7 volts symmetry (duty cycle) r = 1/2, t a = +25 c, recovered clock output, pin 5 v cc = 5 v, v ee = gnd 45 55 % output rise / fall times rise time (t r ) 20%C80% 174 350 500 ps fall time (t f ) 80%C20% 136 315 500 ps clock skew (t rcs ) positive number indicates clock leading data C100 130 250 ps specifications subject to change without notice. (t a = t min to t max , v s = v min to v max , c d = 0.47 m f, unless otherwise noted)
AD808 rev. 0 C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 v input voltage (pin 12 or pin 13) . . . . . . . . . . . . . . v cc + 0.6 v maximum junction temperature . . . . . . . . . . . . . . . . +165 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c esd rating (human body model) . . . . . . . . . . . . . . . . 1500 v notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics: 16-lead narrow body soic package: q ja = 110 c/watt. noise offset overdrive sensitivity input (v) output 1 0 figure 1. input sensitivity, input overdrive dataout 50% (pin 2) clkout 50% (pin 5) setup time hold time t su t h recovered clock skew t rcs figure 2. setup and hold time pin function descriptions pin no. mnemonic description 1 dataoutn differential retimed data output 2 dataoutp differential retimed data output 3v cc2 digital v cc for ecl outputs 4 clkoutn differential recovered clock output 5 clkoutp differential recovered clock output 6v cc1 digital v cc for internal logic 7 cf1 loop damping capacitor 8 cf2 loop damping capacitor 9av ee analog v ee 10 thradj level detect threshold adjust 11 av cc1 analog v cc for pll 12 nin quantizer differential input 13 pin quantizer differential input 14 av cc2 analog v cc for quantizer 15 sdout signal detect output 16 v ee digital v ee for internal logic pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dataoutn dataoutp v cc2 clkoutn clkoutp v cc1 cf1 cf2 v ee sdout av cc2 pin nin av cc1 thradj av ee AD808 ordering guide model temperature range package description package option AD808-622br C40 c to +85 c 16-pin narrowbody soic r-16a AD808-622brrl7 C40 c to +85 c 750 pieces, 7" reel r-16a AD808-622brrl C40 c to +85 c 2500 pieces, 13" reel r-16a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD808 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 C4C AD808 definition of terms maximum, minimum and typical specifications specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. typical specifications are the mean of the distribution of the data for that parameter. if a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribu- tion. this procedure is intended to tolerate production varia- tions: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. for all tested parameters, the test limits are guard- banded to acco unt for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. input sensitivity and input overdrive sensitivity and overdrive specifications for the quantizer in- volve offset voltage, gain and noise. the relationship between the logic output of the quantizer and the analog voltage input is shown in figure 1. for sufficiently large positive input voltage the output is always logic 1 and similarly, for negative inputs, the output is always logic 0. however, the transitions between output logic levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. within this zone of confu- sion, the o utput may be either 1 or 0, or it may even fail to attain a valid logic state. the width of this zone is determined by the input voltage noise of the quantizer (1.5 mv at the 1 10 C10 confidence level). the center of the zone of confusion is the quantizer input offset voltage (1 mv typ). input overdrive is the magnitude of signal required to guarantee correct logic level with 1 10 C10 confidence level. with a single-ended pin-tia (figure 3), ac coupling is used and the inputs to the quantizer are dc biased at some common- mode potential. observing the quantizer input with an oscillo- scope probe at the point indicated shows a binary signal with average value equal to the common-mode potential and instan- taneous values both above and below the average value. it is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the quantizer sensitivity. referring to figure 1, since both positive and negative offsets need to be accommodated, the sensitivity is twice the over- drive. the AD808 quantizer has 4 mv sensitivity typical. with a differential tia (figure 3), sensitivity seems to improve from observing the quantizer input with an oscilloscope probe. this is an illusion caused by the use of a single-ended probe. a 2 mv peak-to-peak signal appears to drive the AD808 quan- tizer. however, the single-ended probe measures only half the signal. the true quantizer input signal is twice this value since the other quantizer input is a complementary signal to the sig- nal being observed. response time response time is the delay between removal of the input signal and indication of loss of signal (los) at sdout. the re- sponse time of the AD808 (1.5 m s maximum) is much faster than the sonet/sdh requirement (3 m s response time 100 m s). in practice, the time constant of the ac coupling at the quantizer input determines the los response time. nominal center frequency this is the frequency at which the vco will oscillate with the loop damping capacitor, c d , shorted. tracking range this is the range of input data rates over which the AD808 will remain in lock. capture range this is the range of input data rates over which the AD808 will acquire lock. static phase error this is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling in- stant, which is assumed to be halfway between the rising and falling edges of a data bit. gate delays between the signals that define static phase error, and ic input and output signals pro- hibit direct measurement of static phase error. data transition density, r this is a measure of the number of data transitions, from 0 to 1 and from 1 to 0, over many clock periods. r is the ratio (0 r 1) of data transitions to bit periods. jitter this is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or unit intervals (ui). jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. jitter on the recovered clock causes jitter on the retimed data. output jitter this is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence (prn sequence). jitter tolerance jitter tolerance is a measure of the AD808s ability to track a jittery input data signal. jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. the pll must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. in order for the vco output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. the modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. hence, the pll can never perfectly track jittered data. however, the magnitude of the phase error depends on the gain around the loop. at low fre- quencies, the integrator of the AD808 pll provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. at frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. the AD808 output will have a bit error rate less than 1 10 C10 when in lock and retiming input data that has the ccitt g.958 specified jitter applied to it. jitter transfer (refer to figure 14) the AD808 exhibits a low-pass filter response to jitter applied to its input data. bandwidth this describes the frequency at which the AD808 attenuates sinusoidal input jitter by 3 db. peaking this describes the maximum jitter gain of the AD808 in db.
AD808 rev. 0 C5C damping factor, z damping factor, z describes the compensation of the second order pll. a larger value of z corresponds to more damping and less peaking in the jitter transfer function. acquisition time this is the transient time, measured in bit periods, required for the AD808 to lock onto input data from its free-running state. symmetryrecovered clock duty cycle symmetry is calculated as (100 on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its 0 level and its 1 level. binary output scope probe AD808 quantizer v cm v cm 4mvp-p input a. single-ended input application binary output scope probe AD808 quantizer v cm v cm 2mvp-p +input Cinput b. differential input application figure 3. (aCb) single-ended and differential input applications 500 v 500 v 5k v 5k v av ee av cc out pin nin a. quantizer differential input stage 6k v thradj av ee 80k v 1.2v +v be b. threshold adjust 30 v v cc1 sdout v ee i ol i oh 30 v c. signal detect output (sdout) 140 v 140 v v cc2 differential output v ee 7.8ma d. pll differential output stagedataout(n), clkout(n) figure 4. (aCd) simplified schematics the AD808 has internal circuits to set the common-mode volt- age at the quantizer inputs pin (pin 13) and nin (pin 12) as shown in figure 4a. this allows very simple capacitive coupling of the signal from the preamp in the AD808 as shown in figure 3. the internal common-mode potential is a diode drop (ap- proximately 0.8 v) below the positive supply as shown in figure 4a. since the common mode is referred to the positive supply, it is useful to bypass the common mode of the preamp to the positive supply as well, if this is an option. note, it is not neces- sary to use capacitive coupling of the input signal with the AD808. figure 14 shows the input common-mode voltage can be externally set.
AD808Ctypical performance characteristics 90000 80000 0 r thresh C v 40000 30000 20000 10000 60000 50000 70000 signal detect voltage C mv 16 6 8 10 12 14 4 figure 5. signal detect voltage vs. r thresh temperature C 8 c C40 95 C20 0 20 40 60 80 8.0 4.0 electrical hysteresis C db 7.5 6.0 5.5 5.0 4.5 7.0 6.5 r th = 5k r th = 7k r th = 0 figure 6. signal detect hysteresis vs. temperature static phase C degrees 0 08 samples 17 25 33 42 50 58 12 8 2 10 6 4 figure 7. histogram of static phase C40 @ 4.4 v rev. 0 C6C los hysteresis C db 0 2.00 2.67 samples 3.33 4.00 4.67 5.33 6.00 6.67 180 120 80 40 20 160 140 100 60 figure 8. histogram los hysteresis 22.1 k w r thresh (all temperature all supply) jitter C degrees 200 0 1.44 1.80 samples 2.16 2.52 2.88 3.24 3.60 3.96 180 120 80 40 20 160 140 100 60 test conditions worst case: C40 8 c figure 9. output jitter histogram jitter frequency C hz 100 10 0.1 1 10m 10 jitter tolerance C ui 100 1k 10k 100k 1m 1 sonet mask 85 8 c 25 8 c C40 8 c figure 10. jitter tolerance vs. frequency
AD808 rev. 0 C7C theory of operation quantizer the quantizer (comparator) has three gain stages, providing a net gain of 350. the quantizer takes full advantage of the extra fast complementary bipolar (xfcb) process. the input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with common- mode voltage as high as the positive supply. the input offset volt age is factory trimmed and is typically less than 1 mv. xfcbs dielectric isolation allows the different blocks within this mixed- signal ic to be isolated from each other, hence the 4 mv sensi- tivity is achieved. traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mv. the AD808 quantizer toggles at 2 mv (4.0 mv sensitivity) at the input without making bit errors. when the input signal is low- ered below 2 mv, circuit performance is dominated by input noise, and not crosstalk. signal detect the input to the signal detect circuit is taken from the first stage of the quantizer. the input signal is first processed through a gain stage. the output from the gain stage is fed to both a posi- tive and a negative peak detector. the threshold value is sub- tracted from the positive peak signal and added to the negative peak signal. the positive and negative peak signals are then compared. if the positive peak, pos, is more positive than the negative peak, neg, the signal amplitude is greater than the threshold, and the output, sdout, will indicate the presence of signal by remaining low. when pos becomes more negative than neg, the signal amplitude has fallen below the threshold, and sdout will indicate a loss of signal (los) by going high. the circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. this means that the input data amplitude needs to reach twice the set los threshold before sdout will signal that the data is again valid. this corresponds to a 3 db optical hysteresis. positive peak detector negative peak detector level shift down level shift up threshold bias pin nin sdout ihys + + AD808 comparator stages & clock recovery pll ithr figure 11. signal level detect circuit block diagram phase-locked loop the phase-locked loop recovers clock and retimes data from nrz data. the architecture uses a frequency detector to aid initial frequency acquisition; refer to figure 12 for a block dia- gram. note the frequency detector is always in the circuit. when the pll is locked, the frequency error is zero and the frequency detector has no further effect. since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition. vco retiming device f det s f det data input 1 s s + 1 recovered clock output retimed data output figure 12. pll block diagram the frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the vco. during the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the vco. these pulses occur on the cycle slips between the data fre- quency and the vco frequency. with a maximum density data pattern (1010 . . . ), every cycle slip will produce a pulse at the frequency detector output. however, with random data, not every cycle slip produces a pulse. the density of pulses at the frequency detector output increases with the density of data transitions. the probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. after the fre- quency error has been reduced to zero, the frequency detector output will have no further pulses. at this point the pll begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). briefly, the measurement of zero phase error does not cause the vco phase to increase to above the average run rate set by the data frequency. the jitter created by a 2 7 C1 pseu- dorandom code is 1/2 degree, and this is small compared to random jitter. the jitter bandwidth for the pll is 0.06% of the center fre- quency. this figure is chosen so that sinusoidal input jitter at 350 hz will be attenuated by 3 db. the damping ratio of the pll is user programmable with a single external capacitor. at 622 mhz, a damping ratio of 5 is obtained with a 0.47 m f capacitor. more generally, the damping ratio scales as (f data c d ) 1/2 . a lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. however, at damping ratios approaching one, the acquisi- tion time no longer scales directly with capacitor value. the acquisition time has two components: frequency acquisition and phase acquisition. the frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop band- width of the pll and is independent of the damping ratio. in practice the acquisition time is dominated by the frequency acquisition. the fractional loop bandwidth of 0.06% should give an acquisition time of 2000 bit periods. however, the actual acquisition time is several million bit periods and is comprised mostly of the time needed to slew the voltage on the damping capacitor to final value.
rev. 0 C8C AD808 1 2 5 6 7 3 4 8 v ee sdout nin av cc1 thradj av ee AD808 pin 16 15 12 11 10 14 13 9 r10 154 v r9 154 v r6 100 v c7 r5 100 v r1 100 v r2 100 v c1 0.1 m f dataoutn dataoutp clkoutn clkoutp c5 0.1 m f c2 0.1 m f r4 100 v r8 100 v r7 100 v r3 100 v c8 r12 154 v tp1 tp2 r11 154 v cd tp7 sdout tp5 tp6 r thresh c11 10 m f c10 gnd r14 49.9 v r15 49.9 v c12 0.1 m f c4 0.1 m f c3 0.1 m f c6 0.1 m f j1 j2 j3 j4 +5v tp3 tp4 note: interconnect run under dut vector pins spaced for rn55c type resistor; component shown for reference only vector pins spaced through-hole capacitor on vector cups; component shown for reference only tp8 j5 c9 r13 301 v r16 3.65k v j6 j7 c13 0.1 m f c14 0.1 m f pin nin 50 v strip line equal length note: c7Cc10 are 0.1f bypass capacitors right angle sma connector outer shell to gnd plane all resistors are 1% 1/8 watt surface mount tpx o test points are vectorboard k24a/m pins dataoutn dataoutp v cc2 clkoutn clkoutp v cc1 cf1 cf2 av cc2 figure 15. evaluation board schematic center frequency clamp (figure 13) an n-channel fet circuit can be used to bring the AD808 vco center frequency to within 10% of 622 mhz when sdout indicates a loss of signal (los). this effectively re- duces the frequency acquisition time by reducing the frequency error between the vco frequency and the input data frequency at clamp release. the n-fet can have on resistance as high as 1 k w and still attain effective clamping. however, the chosen n-fet should have greater than 10 m w off resistance and less than 100 na leakage current (source and drain) so as not to alter normal pll performance. 1 2 5 6 7 3 4 8 16 15 12 11 10 14 13 9 v ee sdout av cc2 pin nin av cc1 thradj av ee dataoutn dataoutp clkoutn clkoutp v cc1 cf1 cf2 v cc2 AD808 n_fet c d figure 13. center frequency clamp schematic rbw: 30hz st: 3.07 min range: r= 0, t= 0dbm div 20.00m c d peak 0.047 0.11 0.10 0.07 0.47 0.04 div 36.00m start stop 500.000hz 100 000.000hz figure14. jitter transfer vs. c d
AD808 rev. 0 C9C using the AD808 acquisition time this is the transient time, measured in bit periods, that required for the AD808 to lock onto the input data from its free running state. ground planes the use of one ground plane for connections to both analog and digital grounds is recommended. power supply connections the use of a 10 m f capacitor between v cc and ground is recom- mended. the +5 v power supply connection to v cc2 should be carefully isolated. the v cc2 pin is used inside the AD808 to provide the clkout and dataout signals. use a 0.1 m f decoupling capacitor between ic power supply input and ground. this decoupling capacitor should be posi- tioned as closed to the ic as possible. refer to the schematic in figure 15 for advised connections. transmission lines use 50 w transmission line for pin, nin, clkout, and dataout signals. terminations use metal, thick-film, 1% termination resistors for pin, nin, clkout, and dataout signals. these termination resistors must be positioned as close to the ic as possible. use individual connections, not daisy chained, for connections from the +5 v to load resistors for pin, nin, clkout, and dataout signals. loop damping capacitor, c d a ceramic capacitor may be used for the loop damping capaci- tor. us ing a 0.47 m f, 20% capacitor provides < 0.1 db jitter peaking. AD808 output squelch circuit a simple p-channel fet circuit can be used in series with the output signal ecl supply (v cc2 , pin 3) to squelch clock and data outputs when sdout indicates a loss of signal (figure 16). the v cc2 supply pin draws roughly 72 ma (14 ma for each of 4 ecl loads, plus 16 ma for all 4 ecl output stages). this means that selec tion of a fet with on resistance of 0.5 w will affect the common mode of the ecl outp uts by only 36 mv. 1 2 5 6 7 3 4 8 16 15 12 11 10 14 13 9 v ee sdout av cc2 pin nin av cc1 thradj av ee dataoutn dataoutp clkoutn clkoutp v cc1 cf1 cf2 v cc2 AD808 to v cc1 , av cc , av cc2 p_fet bypass cap 5v figure 16. squelch circuit schematic
rev. 0 C10C AD808 outline dimensions dimensions shown in inches and (mm). 16-lead small outline ic package (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 8 0 8 0.0196 (0.50) 0.0099 (0.25) x 45 8
C11C
printed in u.s.a. c3262C8C1/98 C12C

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